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TH6503 usb low-speed interface rev. 3.5 dec 2000 description the TH6503 is an integrated circuit which enables the universal serial bus (usb) to be connected to a microcontroller. the interface module contains all the components required to transmit data via the usb. the TH6503 has been developed for applications requiring a low speed interface to the usb. any microcontroller can be used for control purposes. in addition to the default endpoint 0 for control transfer up to two endpoints can be supported by TH6503. the TH6503 has been developed in conformity with usb specifications 1.1. features ? complient with usb specification 1.1 ? supports up to three programmable endpoints for interrupt and control transfer in each direction ? data transfer at usb low speed ? supports suspend mode ? universal serial microcontroller interface ? register programmable ? programmable 1.5 mhz to 6 mhz out clock for microcontroller ? provides power supply for the microcontroller (3.3 volts or 5 volts) ? integrated oscillator for clock generation, supports 6 mhz quartz, ceramic resonator or external clock input ? s imple external circuitry TH6503 sample application figure 1. typical TH6503 sample application figure 1 demonstrates a typical TH6503 applica- tion. the TH6503 translates the data and control signals received from the usb in a serial format which can be read by the microcontroller. the data is stored in a fifo buffer and can be called up from a standard microcontroller via a register program- mable serial interface at any time and processed further. data generated by peripheries is passed to the TH6503 with the same protocol and stored in a fifo buffer until it is collected by the usb. the TH6503 translates all the data in the usb-specific format and generates the necessary control sig- nals. the TH6503 requires a minimum number of external elements and can easily be implemented in a circuitry. it provides an external clock which can be used to activate a microcontroller. micro- controller/ customer application to usb host / hub usb interface serial interface oclk /orst TH6503
2 TH6503 usb low-speed interface function usb data transmission the TH6503 supports the usb specification 1.1 data model. data from the usb host to the device and vice versa is transmitted serially. the data are nrzi coded to increase transmission reliability; bit stuffing (inserting an extra 0 bit after any 6 consecutive 1 bits) is performed and a crc check carried out. bit stuffing, nrzi coding/decoding and crc checks or generation are performed within the TH6503. the data is transmitted in packets. three types of packets are defined for the usb: token, data and handshake. the token is always passed on by the host. it contains a pid (packet identifier) which defines the direction of the following data transmission and the address of the device and endpoints to be ad- dressed. depending on the previous token command, data is transferred from the usb host to the TH6503 (out transfer) or transferred from the TH6503 to the usb host (in transfer). in the process the respective fifos are written (out) or read (in ). the data transfer is concluded with a handshake. if the data has been received successfully, an ack is sent to the data source. if no data is ready for an in transfer out of the TH6503, it sends an nak handshake instead of the data (if endpoint is ena- bled). TH6503/ microcontroller cooperation figure 2. data flow the TH6503 is responsible for the data flow be- tween the usb and the microcontroller. it ensures that the usb transfers the data in line with the protocol. all information in the protocol layer is decoded by the TH6503 and carried out accord- ingly. the data arriving from the usb host is stored in a fifo buffer until it is collected by the microcontroller. data transmitted to the usb host are imported from a fifo buffer which has previously been filled by the microcontroller. a /int signal signals to the microcontroller that the fifo status has been changed by usb. data is transferred between the microcontroller and the TH6503 via a software-emulating serial interface controlled by the microcontroller. as the TH6503 cannot interpret the content of the data, it must be evaluated within the microcontroller. this also applies to usb-specific control informa- tion. all usb-typical descriptors and the associ- ated requests must be created and managed by the microcontroller. the setting of the usb address serves here as an example. after resetting the usb, the address is set to the default value 0 (usbaddressregister). a specific address is transferred from the usb host software to the device with the set_address command. this command, like all set and get commands, can only be decoded by the micro- controller. the usb address is decoded in the TH6503 with the aid of the usb addressregister. for this reason the microcontroller must write the usb address determined in this register. the TH6503 supports the usb suspend mode. control takes place via the microcontroller. the act bit can be used in the statusregister <5> which is set on the usb for each activity. if this bit has been inactive for a longer period of time (3 ms), the microcontroller can set the TH6503 and itself in the suspend mode using the sus bit in the bridgeconfigregister <4>. the suspend mode can be ended using the software or an external signal. apart from the suspend mode, the TH6503 also supports a number of other power saving modes which either stop the microcontroller by switching off the clock or set the whole usb bridge in a power saving mode. the TH6503 provides the clock pulse for the microcontroller. it can be programmed with the ocr 1 - ocr 0 bits in the bridgeconfigregister <1-0>. the TH6503 supplies 3.3v voltage to power the microcontroller; this is produced by the adjacent 5v bus power supply connection. t h 6 5 0 3 u s b i n t e r f a c e t o u s b h u b / h o s t e n d p o i n t 0 e n d p o i n t 1 e n d p o i n t 2 i n t e r r u p t t r a n s f e r c o n t r o l t r a n s f e r s e r i a l d a t a m i c r o - c o n t r o l l e r v e n d o r s p e c i f i c d a t a i n p u t d e v i c e
3 TH6503 usb low-speed interface figure 3. TH6503 block diagram microcontroller interface the data is transferred between the microcontroller and the usb bridge using the clock (sck) generated by the microcontroller asynchronous to the usb clock. data in transfer (from the microcontroller to the TH6503) data in transfer is initiated with rising sin edge (in packet sync). data is transferred via the sdi pin. initially the adr/cntinregister which indicates the internal address in the TH6503 is written. data is subsequently transferred beginning with byte 0 to byte n lsb first. bits ic3-ic0 in the adr/cntinregister <3-0> contain the information on the number of bytes to be transferred to the usb host if the target of the data transfer was an in fifo. a zero data transfer is identified with reset of ic3- ic0 bits after writing the adr/cntinregister one additional clock on sck must be generated. if a register is the target of the data in transfer the bits ic3-ic0 and ti have no meaning. with falling sck edge the microcontroller trans- mit the bits to sdi and the bits are imported from the bridge with increasing sck edge. after each transmission of 8 bits the respective in fifo value is increased by 1. if the microcontroller writes more data than indicated in the adr/cntinregister, the oldest data are overwritten. after the final falling edge of sck first sdi and then sin must be reset to 0 to terminate the transfer. the associated in done bit in the statusregister is reset automati- cally to enable usb in transfer. TH6503/ microcontroller cooperation (continued) usb i/o oclk v3.3 d+ d- sie serial interface engine vbus gnd status signals control signals bus interface wake r e s e t oscillator/ divider sck sin sdi sdo 13 12 11 10 15 8 16 6 7 4 3 2 1 5 power supply 3.3v 14 /orst 1k5 10 micro- controller interface v3.3
4 TH6503 usb low-speed interface figure 4. serial data in data out transfer (from the TH6503 to the microcontroller) an impulse on the sdi link at sin = 0 represents the out packet sync for an out transfer. with the falling sck edge the data (lsb first) is shifted to sdo and with rising sck edge accepted by the microcontroller. the statusregister is transferred initially followed by the cntoutregister and finally the out fifo data. if the transfer is terminated after less than 8 clock pulses, only single statusregister bits are read. linear transfer is interrupted by sin = 1 and must be initiated with a new out packet sync at sin = 0. two impulses on the sdi link initiate a transfer of the cntoutregisters and of the following out fifo bytes without the statusregister. a zero data transfer is identified by an out count byte value of 0. the end of a data out transfer clears the set bit in the cntoutregister and the od bit in the statusregister to make the next usb out or setup transfer possible. figure 5. out transfer of statusregister microcontroller interface (continued) 0 1 0 1 0 1 0 1 sck sin sdo sdi 0 1 n status0 status1 status2 status n /int microcontroller latches data on rising edge of sck bridge shifts data on falling edge of sck end of transfer clear interrupt latch sdi pulse with sin=0: - copy statusregister to shift register for serial data out any break after identify the /int source possible n <= 7 0 1 0 1 0 1 0 1 sck sin sdo sdi 0 1 7 n+8 /int bridge latches data on rising edge of sck microcontroller shifts data on falling edge of sck end of in transfer microcontroller outputs adr/cntinregister bit 0 / ac0 on sdi ac7 data bit 0 bit n ac0 ac1 ac2
5 TH6503 usb low-speed interface figure 6. complete data out transfer figure 7. out transfer, only cntoutregister and out fifo bytes interrupt function if sin = 1, the sdo pin can be used to generate an interrupt signal. the interrupt is low active. it is triggered if a control transfer is made from the usb host or a control or interrupt transfer is made to the usb host and one of the id12, id0 or od bits has been set in the statusregister <3-1> or at high level of the wake pin. an interrupt signal is also triggered on resume and usb_reset. the interrupt latch is reset on reading the status register. if an interrupt is generated during read- ing statusregister, this interrupt is latched and the interrupt source is after new statusregister reading visible. a wake interrupt is only generated during the stop state (bits so and/or smc in the bridgeconfig register are set). microcontroller interface (continued) 0 1 0 1 0 1 0 1 sck sin sdo sdi 0 1 7 15 n+16 status0 status1 status2 status7 cnt0 cnt7 fifo bit 0 bit n /int microcontroller latches data on rising edge of sck bridge shifts data on falling edge of sck end of out transfer (out tranfer after reading the status -and cntoutregister with sin=0 clears ep0 out done bridge outputs next register (cntoutregister) bit 0 on sdo clear interrupt latch sdi pulse with sin=0: - transfer statusregister to serial data out 0 1 0 1 0 1 0 1 sck sin sdo sdi 0 7 n+8 microcontroller latches data on rising edge of sck bridge shifts data on falling edge of sck end of out transfer (out tranfer > 8 clocks the status -and cntoutregister with sin=0 clears ep0 out done bridge outputs next register (fifo) bit 0 on sdo two sdi pulses with sin=0: - transfer cntoutregister and out fifo bytes to serial data out cnt0 cnt1 cnt7 fifo bit 0 bit n /int
6 TH6503 usb low-speed interface t 3 t 4 t 5 t 13 sck sin sdo sdi t 12 t 14 t 15 t 16 t 17 bit 0 bit n t 2 t 1 timing serial interface figure 8 and figure 9 show the timing of the serial interface of the TH6503. the serial interface is controlled by a standard microcontroller. it can be connected with any microcontroller port. figure 8. timing serial data in figure 9. timing serial data out t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 sck sin sdo sdi /int bit 0 bit n
7 TH6503 usb low-speed interface input signals are double buffered and digital filtered. therefore all spikes with a width < 255 ns are suppressed. timing serial interface (continued) description [1] symbol unit min typ max general oscillator input period on osc1 ns 164 170 rising time of sdo t 1 ns 20 falling time of sdo t 2 ns 7 sck period t 3 ns 600 step high time sck [2] t 4 ns 345 low time sck [2, 3] t 5 ns 255 data in setup time of sck after rising edge of sin t 6 ns 170 hold time of sin after last rising edge of sck t 7 ns 170 setup time of int-signal after rising edge of sin t 8 ns 200 hold time of int-signal after falling edge of sin t 9 ns 165 setup time of data on sdi before rising edge of sck t 10 ns 170 hold time of data on sdi after falling edge of sck t 11 ns 0 data out setup time of sdi-pulse after falling edge of sin t 12 ns 170 setup time of sin after last falling edge of sck t 13 ns 170 high time of sdi-pulse t 14 ns 255 setup time of data on sdo after falling edge of sdi-pulse t 15 ns 280 setup time of sck after falling edge of sdi-pulse t 16 ns 170 setup time of data on sdo after falling edge of sck t 17 ns 365 notes: [1] capacitive load of 50 pf [2] can be asymmetrical [3] the low time of sck between the last bit of a byte and the first bit of the next byte must be at least 510 ns.
8 TH6503 usb low-speed interface connecting the TH6503 with a microcontroller the TH6503 can be connected with any micro- controller via a serial interface. the serial outputs can be connected with any microcontroller ports. the TH6503 out clock can be used to provide the clock pulse supply to the microcontroller. the reset output is low active and configured in an open drain structure. for this reason the output must be set at a defined level with external v 3.3 resistance. figure 12. the connection between the TH6503 and the 80c51 by intel figure 13. the connection between the TH6503 and the pic16c54 by microchip figure 10. the connection between the TH6503 and the mc6805 by motorola figure 11. the connection between the TH6503 and the z86kxx by zilog sck /orst oclk sdo sdi sin TH6503 13 12 11 10 15 14 pa0 /reset xosc1 pa3 pa2 pa1 xosc2 mc6805 v 3.3 sck /orst oclk sdo sdi sin TH6503 13 12 11 10 15 14 p24 /reset xtal1 p27 p26 p25 xtal2 z86kxx v 3.3 sck /orst oclk sdo sdi sin TH6503 13 12 11 10 15 14 p1.0 rst xtal1 p1.3 p1.2 p1.1 xtal2 80c51 v 3.3 sck /orst oclk sdo sdi sin TH6503 13 12 11 10 15 14 ra0 /mclr osc1 ra3 ra2 ra1 osc2 pic16c5x v 3.3
9 TH6503 usb low-speed interface application wiring diagram figure 14 shows a sample application circuitry with the TH6503 and a mc68hc05. to stabilize the internal power supply the v3.3 pin must always be connected with an 10 capaci- tor. figure 14. sample wiring diagram to connect the TH6503 with an mc68hc05 wake function the usb specification defines that a device has to go into suspend mode if no bus traffic was de- tected for ca. 3 ms. after the device is set to suspend mode, the wake pin can be used to wake up the device with an external event. if the wake pin is connected with an rc-element, the TH6503 wakes up after the time defined by the rc-element. this feature can be used to check for data in periodical time frames. reset output the reset output (/orst) of the TH6503 can be connected with the reset input of the microcontroller. it?s a low active signal. this signal has a minimum length of 31 clock cycles with a default frequency of 1.5 mhz (see pin description for details). after this reset pulse the microcontroller can reseted but it must wait to programming the TH6503 until the usb reset is inactive. all register of TH6503 will be held in reset state, exept the statusregister, until the corresponding bits hwr or res is cleared.
10 TH6503 usb low-speed interface register description the statusregister, cntoutregister and the out fifo can only be read by the microcontroller. the internal registers of the TH6503 can only be written by the microcontroller. statusregister (read only) always the first byte of a data out transfer is loaded in the out shift register with the falling edge of an pulse on sdi with sin=0 bit number bit mnemonic reset status function 7 hwr 1 hardware reset ? ? is set if the reset source is por, reset pin or low voltage reset is reset automatically on reading the statusregister and also by the following sw-reset before reading the statusregister 6 res 0 usb reset ? ? ? is set so long as a reset is received on the usb (sw reset) is reset automatically on reading the statusregister and also by the following hw-reset before reading the statusregister the reset of this bit enables ep0 out and ep0 in (eo0 and ei0 bits in the serialflag register are set) 5 act 0 usb activity ? ? ? ? is set when the usb is active (all bus states exept idle) is reset automatically on reading the statusregister can be used by the microcontroller to calculate the suspend time if set the so and smc bits in the bridgeconfigregister are reset 4 rdt 0 usb resume detect ? ? ? is set automatically if a resume status has been decoded is reset automatically if the resume status has been terminated if set the so and smc bits in the bridgeconfigregister are reset 3 id12 0 ep1/2 in done ? ? is set if the data requested by an in token have been completely transmitted to the usb host and an ack has been received is reset with the falling sin edge (end of in transfer) 2 id0 0 ep0 in done ? ? is set if data requested by an in token have been completely transmitted to the usb host and an ack has been received is reset with the falling sin edge (end of in transfer) 1 od 0 out done ? ? is set automatically if the data are complete in the fifo after a valid setup or out token has been received and an ack has been sent to the usb host is reset with the rising sin edge (end of out transfer) 0 wa 1 wake activity ? ? is set and reset automatically depending on the voltage level at the wake pin is an inverted copy of the wake pin and can be used as low active interrupt output, when sin = 1
11 TH6503 usb low-speed interface cntoutregister (read only) second byte of each out transfer following an out packet sync adr/cntinregister (write only) first byte of each data in transfer following the in packet sync register description (continued) internal register bit number bit mnemonic reset status function 7-6 oa 0 out address ? ? last valid out endpoint indicates the endpoint of actual out fifo data 00 ep0 01 ep1 10 ep2 only valid if ep1 out or ep2 out enabled, otherwise the internal revision number is visible 5 to 0 toggle out ? ? is set if the data packet pid was data1 and reset if the data packet pid was data0 is latched with a valid ep0 setup or a out token 4 set 0 setup ? ? ? ? ? is set if a setup token is received is reset after out transfer to microcontroller no stall or nak is sent because it is not permitted on the setup token the so0 and si0 (stall ep0) flags in the usbflagregister are reset on rising edge of setup a setup token flash all in fifos 3-0 oc3-0 0 ep0 out byte count ? ? amount of out data received in the ep0 fifo in bytes applicable values from 0 to 8 a zero data transfer is identified 0 bit number bit mnemonic reset status function 7 ti 0 toggle in ? is set if the data packet pid is data1 and reset if the data packet pid is data0 6-4 ra2-0 0 internal address destination address for a write operation to a TH6503 register or in fiifo 3-0 ic3-0 0 in byte count ? ? number of data bytes to be transmitted without adr/cntinregister from the microcontroller to the TH6503 if the destination address was an in fifo applicable values from 0 to 8 0 indicates a zero data transfer to the usb host, but blocks the infifo until ack is received
12 TH6503 usb low-speed interface ep0/1/2 fifo (write only) internal address: b000, b001 or b010 size: 8 bytes the device user data is stored temporarily at this location for transfer to the usb host. ? the address b000 indicates a data transfer from ep0 ? the address b001 indicates a data transfer from ep1 ? the address b010 indicates a data transfer from ep2 ? only one of the three addresses may be used at any one time; fifo is used alternately, de- pending on the device function ? will be flushed with a new setup token for as long as bit set in cntoutregister is set serialflagregister (write only) internal address: b100 size: 8 bits all endpoints must remain deactivated until usb reset has been decoded (statusregister <6>). register description (continued) bit number bit mnemonic reset status function 7-6 x 0 reserved - must be set to 0 5 eo2 0 enable ep2 out ? ? activate endpoint 2 out microcontroller can set the bit after detecting a usb reset in order to enable data transfers from the usb host via ep2 if set the cntout register bit <7-6> indicates the source of the last out transfer binary coded 4 eo1 0 enable ep1 out ? ? activate endpoint 1 out microcontroller can set the bit after detecting a usb reset in order to enable data transfers from the usb host via ep1 if set the cntout register bit <7-6> indicates the source of the last out transfer binary coded 3 ei2 0 enable ep2 in ? activate endpoint 2 in microcontroller can set the bit after detecting a usb reset in order to enable data transfers to the usb host via ep2 2 ei1 0 enable ep1 in ? activate endpoint 1 in microcontroller can set the bit after detecting a usb reset in order to enable data transfers to the usb host via ep1 1 ei0 0 enable ep0 in ? activate endpoint 0 (in transfer) is set automatically after detecting a usb reset to enable in control transfers to the usb host 0 eo0 0 enable ep0 out ? activate endpoint 0 (out transfer) is set automatically after detecting a usb reset to enable out control transfers to the usb host
13 TH6503 usb low-speed interface usbflagregister (write only) internal address: b101 size: 8 bits register description (continued) usbaddressregister (write only) internal address: b110 size: 8 bits bit number bit mnemonic reset status function 7 fi2 1 flush ep2 in ? ? clears ep2 fifo is set and reset automatically depending on the actual fifo status must be set before ep2 of the ep1/2 fifo can be overwritten by the microcontroller 6 fi1 1 flush ep1 in ? ? clears ep1 fifo is set and reset automatically depending on the actual fifo status must be set before ep1 of the ep1/2 fifo can be overwritten by the microcontroller 5 fi0 1 flush ep0 in ? ? clears ep0 fifo is set and reset automatically depending on the actual fifo status must be set before the ep0 fifo can be overwritten by the microcontroller 4 bo0 0 busy out ? ? ? blocks the ep0 out fifo for the usb host is set and reset automatically depending on the actual fifo status TH6503 responds with no handshake for a usb host setup token or with a nak signal for an out token (nak state) to leave the nak state, the microcontroller does an outfifo read (the microcontroller rereads the last data) 3 si2 0 stall ep2 ? ? sets ep2 to stall TH6503 responds with a stall for a usb host in or out token if address and ep2 have been decoded only operative if ep2 is active 2 si1 0 stall ep1 ? ? sets ep1 to stall TH6503 responds with a stall for a usb host in or out token if address and ep1 have been decoded only operative if ep1 is active 1 si0 0 stall ep0 in ? ? sets ep0 in to stall TH6503 responds with a stall for a usb host in token if address and ep0 have been decoded will be cleared after setup token 0 so0 0 stall ep0 out ? ? ? sets ep0 out to stall TH6503 responds with a stall for a usb host out token if address and ep0 have been decoded stall is inoperative for a setup token from the usb host setup clears stall ep0 in and stall ep0 out bits bit number bit mnemonic reset status function 7 x 0 reserved 6-0 ad6-0 0 usb device address ? ? usb address entered by microcontroller zero after reset microcontroller must decode the address from descriptor data after a setup (set_address) token and write it in this register
14 TH6503 usb low-speed interface bridgeconfigregister (write only) bits only take effect after the data in transfer has been completed. internal address: b111 size : 8 bits register description (continued) bit number bit mnemonic reset status function 6 os 0 oclk static ? ? ? ? is set and reset by microcontroller if set the oclk pin drives a static level on the oclk pin, this level depends on the smc bit in the bridgeconfigregister os smc oclk output 0 0 clock, programmed by ocr<1-0> bits 0 1 0 1 0 0 1 1 1 can be used as ending stop state signal for an external microcontroller with own clock works like a low active interrupt 5 fr 0 force resume ? ? ? terminates suspend mode is set by microcontroller if data is sent from connected device the TH6503 signals a resume to the usb host the timing (10-15 ms) of the resume state must be done by microcontroller 4 sus 0 suspend ? ? sets the TH6503 in suspend mode should be set by the microcontroller if no bus traffic is detected for longer than 3 ms can be set and reset by microcontroller only 3 so 0 stop oscillator ? ? stops the microcontroller and the usb bridge (the smc bit is set automatically) is set by the microcontroller is reset by an external wake up signal, usb activity or reset 2 smc 0 stop microcontroller clock ? ? ? stops the microcontroller is set by the microcontroller is reset by an external wake up signal, usb activity or reset only affects the oclk pin 1-0 ocr1-0 0 0 out clock rate output frequency on the oclk pin 0 0 1.5 mhz (default) 0 1 2.0 mhz 1 0 3.0 mhz 1 1 6.0 mhz, without guarantee of symmetry, it depends on the quality of the oscillation element
15 TH6503 usb low-speed interface flowchart for programming the TH6503 main program figure 15 shows the main order of events of the usb specific part of firmware for the microcontroller. the bits located in the statusregister mark the event. depending on these bits the firmware must branch. figure 15. flowchart for main program (using TH6503 in interrupt mode) initialisation sck=0;sin=1; sdi=0 out done ep0 in done ep1/2 in done no sdo=1 no yes read cntoutregister and out fifo yes data to send ? yes no yes data to send ? yes yes reaction (depends on the received data) write next control byte(s) to in fifo write next device data to in fifo read statusregister no no usb active yes reset suspend timer no resume detect reset sus bit in the bridgeconfigregister yes no usb reset yes
16 TH6503 usb low-speed interface reading the statusregister the reading of the status register is the first action of the microcontroller. the TH6503 stores the information on what?s happened on the usb in this register figure 16. reading the statusregister flowchart for programming the TH6503 (continued) read statusregister generating a pulse on sdi sin=0 generating a rising edge on sck to save bit on sdo generating a falling edge on sck to shift next bit to sdo more bits to read ? yes no save sdo bit abort transfer with sin=0
17 TH6503 usb low-speed interface reading the cntoutregister and out fifo if the out done bit in the statusregister is set, the microcontroller must receive the data collected from the out fifo. figure 17. reading the cntoutregister and out fifo flowchart for programming the TH6503 (continued) read cntoutregister and out fifo generating a rising edge on sck save sdo bit more bits to read ? generating a falling edge on sck to shift the next bit to sdo no yes abort transfer with sin = 1 continue after reading statusregister (see fig.6 and fig 7 on page 5)
18 TH6503 usb low-speed interface reaction on the fifo data after the microcontroller has collected the fifo data, the microcontroller must decode the fifo data and reacts appropriately. figure 18. reaction on the received data flowchart for programming the TH6503 (continued) reaction setup bit = 1 ? yes decoding fifo data, reaction depends on the request (see usb spec rev. 1.1, chapter 9)
19 TH6503 usb low-speed interface write next device data to TH6503 if in fifo data has to be sent to the usb host the microcontroller must wait until the corresponding in done bit is set (in fifo is empty). then the microcontroller can store the next data in the in fifo. figure 19. writing next device or control data to in fifo flowchart for programming the TH6503 (continued) output first bit on sdi sin=1 generating a rising edge on sck to latch bit by bridge more bits to write ? generating a falling edge on sck and output the next bit on sdi no yes write next device data to in fifo 1 or 2 end of in transfer sin=0 and sck=0 write next control byte(s) to in fifo 0 write adr/cntinregister write internal register
20 TH6503 usb low-speed interface electrical characteristics all voltage values are referenced to gnd (gnd = 0 v). all values are based on the usb specifi- cation v1.1. if any value is unspecified, the value from the usb specification v1.1 is valid. absolute maximum ratings recommended operational conditions parameter symbol min max unit dc supply voltage v dd - 0.3 7.0 v input voltage v in - 0.3 v3.3 + 0.3 v input current i in - 10 10 ma storage temperature range (ceramic) t stgc - 65 150 c storage temperature range (plastic) t stgp - 40 125 c power dissipation (sop16) p d 600 mw parameter symbol min typ max unit dc supply voltage v dd 4.40 5.00 5.25 v operating temperature range t a 0 70 c junction temperature t j < 150 c operating frequency f op 6.00 mhz
21 TH6503 usb low-speed interface static characteristics electrical characteristics parameter symbol condition [4] min typ max unit power supply voltage v 3.3 3.00 3.30 3.60 v power supply current i 3.3 60 ma stand-by current [5] i stb 80 150 a voltage input low v ilcmos 0.3*v 3.3 v voltage input high v ihcmos 0.7*v 3.3 v schmitt trigger, positive going threshold v t+cmos 2.4 v schmitt trigger, negative going threshold v t-cmos 0.8 v hysteresis, schmitt trigger (vt+ ? vt-) v hyscmos v il to v ih ,v ih to v il 0.5 v differential input sensitivity v di |(d+)-(d-)| 0.2 v differential common mode range v cm includes v di 0.8 2.5 v single ended receiver threshold v se 0.8 2.0 v single ended receiver hysteresis v hyse 0.1 v input low current i il v in = gnd -10 10 a input with pullup i ilu v in = gnd -50 -21.0 -7 a input high current i ih v in = v3.3 -10 10 a input with pulldown i ihd v in = v3.3 7 22.9 65 a voltage output low v ol i ol = 1 ma 0.4 v voltage output high v oh i oh = 1 ma 2.4 v current output i o 1 ma differential output low v old r l of 15 kohm to gnd 0.3 v differential output high v ohd r l of 1.5 kohm to 3.6 v 2.8 3.6 v hi-z output leakage current i oz v in = gnd or v3.3 -10 10 a notes: [4] specified at vdd = vbus = 4.40v to 5.25v and tested at room temperature only [5] differential transceiver fs in suspend mode, tested without pull-down and pullup resistors on the d- and d+ data line
22 TH6503 usb low-speed interface pin description pin description usb interface 1 vbus i adjacent 5v bus voltage 5 gnd i ground 4 d+ i/o usb data 3 d- i/o usb data ? must be connected via 1.5 kohm resistor to 3.3 v for low speed devices microcontroller interface 13 sck i serial clock (generated by microcontroller) ? ? ? ? out transfer: sdo is accepted by the microcontroller in high status or with falling sck edge. the usb bridge shifts the next bit to sdo in low status or with rising edge. in transfer: sdi is accepted by the usb bridge in high status or with falling sck edge. the microcontroller shifts the next bit to sdi in low status or with rising edge. internal pulldown 12 sin i serial input direction (generated by the microcontroller) ? ? ? ? ? specifies the direction of the data transfer and marks the end of a fifo transfer sin = 0: data is sent from the usb bridge to the microcontroller via sdo. an out packet sync for the statusregister or cntoutregister can be triggered via sdi. a rising edge terminates a status or out transfer and the usb out done status bit is cleared. sin = 1: data is sent from the microcontroller to the usb bridge via sdi. sdo emits an /int signal. a falling edge terminates an in transfer and the ep0 in done or ep1/2 in done status bit is cleared if the destination address is a fifo address. rising edge indicates the commencement of an in transfer (in packet sync). the in is started once sck is pulsed. the adr/cntinregister is transferred initially. internal pulldown 11 sdi i serial data in (from the microcontroller to the usb bridge) ? ? ? ? generated by the microcontroller sin = 0: the falling edge from a single sdi impulse loads the first bit (lsb first) of the statusregisters to sdo. the statusregister can be read. two sdi impulses load the first bit of the cntoutregister. sin = 1: sdi transfers the serial data. internal pulldown 10 sdo o serial data out (from the usb bridge to the microcontroller) ? ? ? ? generated by the usb bridge sin = 0: sdo show the status of bit 0 of the statusregister (wa) and after a sdi pulse sdo transfers the serial data. sin = 1: sdo is used to generate the /int signal which can be used to control the microcontroller interrupt /int: - low active signal to sdo at sin 1 - is a nor connection of the resume signal, usb reset and an interrupt latch - interrupt latch is set for all increases in outdone, ep0 in done and ep1/2 in done edge. - interrupt latch is reset, if the statusregister is read (sdi impulse at sin= 0). 15 oclk o clock out for microcontroller (programmable frequency) 14 /orst open drain reset out (hw- or sw reset) ? ? ? ? ? ? orst=0 reset state orst=1 normal operation must be connected with an external pullup resistor (to v3.3) all resets are indicated on this pin this type of reset can be determined by evaluating the bits hwr or res in the statusregister <7> or <6> reset conditions: - internal por - reset pin - min. 20s (31 oclk cycles at 1.5 mhz) or as long as the reset pin is active - low voltage reset if vbus<3.3v 10% with a minimum of 20 s (31 oclk cycles at 1.5 mhz) or as long as vbus < 3.3v - usb-reset - reduced to 20 s (31 oclk cycles at 1.5 mhz), the end of a usb reset is indicated by a rising edge of /int and by cleared res bit in the statusregister miscellaneous 6 osc1 i oscillator in for a quartz, ceramic resonator or external clock input, 6 mhz 1.5% 7 osc2 o oscillator out 8 wake i ? ? ? ? if a specific high trigger level is reached (schmitt trigger characteristic) the usb bridge oscillator is restarted and the so and smc bit in the bridgeconfigregister is cleared. it may be connected to an rc element to achieve restart cycles from 50 to 100 ms the input signal is compatible with large slew rate if the so or smc bit in the bridgeconfigregister is set a rising edge on the wake pin generates an interrupt signal on sdo, when sin = 0 16 /reset i reset input with schmitt-trigger characteristic (internal pullup) 2 v3.3 o 3.3 v output must be connected with an external capacitor (approx. 10) 9 test i ? test pin, internal pulled up (do not connect to external circuitry)
23 TH6503 usb low-speed interface pinout information (top view) package information (sop 16 wb) the TH6503 is available in a sop 16 wb package. 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 v b u s r e s e t o c l k / o r s t s c k s i n s d i s d o t e s t v 3 . 3 d - d + g n d o s c 1 o s c 2 w a k e t h 6 5 0 3 the TH6503 usb low-speed interface is available in a 16 pin sop wb package. the order number is TH6503 . ordering information 1 2 3 d e h b e a 1 a l ? quality data quality data is available on request. contact: thesys mikroelektronik produkte gmbh quality assurance haarbergstr. 67, 99097 erfurt, germany tel.: +49-361-4276155, fax: +49-361-4276060 small outline package (sop) sop 16 wide body (wb) package type d e h a a 1 e b l ? package code sop wb 16 min max 0.398 0.413 0.283 0.300 0.393 0.419 0.091 0.111 0.002 0.014 0.05 0.013 0.020 0.012 0.050 10 df16 dimensions in inches, coplanarity < 0.004", original dimension: inch sop wb 16 min max 10.11 10.49 7.19 7.62 9.98 10.64 2.31 2.82 0.05 0.36 1.27 0.33 0.51 0.30 1.27 10 df16 dimensions in millimeters, coplanarity < 0.1 mm, original dimension: inch
24 TH6503 usb low-speed interface this data sheet is printed on environmentally friendly paper, bleached without chlorine. 10lt.155e important notice devices sold by melexis are covered by the warranty and patent indemnification provisions appearing in its term of sale. melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. melexis reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with melexis for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommende d without additional processing by melexis for each application. the information furnished by melexis is believed to be correct and accurate. however, melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of melexis? rendering of technical or other services. ? 1998 melexis gmbh. all rights reserved. for the latest version of this document, go to our website at: www.melexis.com or for additional information contact melexis direct: ? usa melexis inc. 41 locke road concord, nh 03301 usa phone: +1 603 223 2362 fax: +1 603 223 9614 email: sales_usa@melexis.com ?? germany melexis gmbh schiess strasse 55 d-40549 dusseldorf, germany phone: +49 211 536-02-0 fax: +49 211 536-02-50 email: sales_de@melexis.com ? france melexis france tour arago, 5 rue bellini 92806 puteaux la defense france phone: +33 147 78 11 34 fax: +33 147 78 06 35 email: sales_france@melexis.com ? japan star electronics co., ltd 1-14-10 shiba minato-ku, tokyo phone: +81 3 3452 7171 fax: +81 3 3769 2197 email: sales_japan@melexis.com ? united kingdom silicon concepts pcb lynchborough road hampshire gu30 7sb united kingdom phone: +44 1428 751 617 fax: +44 1428 751 603 email: sales_uk@melexis.com ? taiwan beechwood int?l taiwan co. room 8, 17floor, no.189, sec 2 keelung road taipei, taiwan phone: +886 2 2739 3322 fax: +886 2 2739 3090 email: sales_taiwan@melexis.com ? korea neos korea rm 205 chungho plaza, 668-9 deungchon-dong, kangse-ku seoul 157-030 phone: +82 2 3665 6527 fax: +886 2 3665 6529 email: sales_korea@melexis.com worlwide sales offices

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